Jashwanth Bamidi

FPGA & digital Built · controlled demonstration

FPGA Orderbook Engine

Hardware that reads market-style packets and keeps an up-to-date best bid and ask.

Role
RTL and SoC integration
When
2026
Tools
SystemVerilog, Spartan-7, MicroBlaze, AXI4-Lite, Vivado, Vitis, Python
MicroBlazeC traffic generatorAXI4-Litebyte writesInjector FIFOdata + lastEthernetEtherType 0x0800IPv4protocol UDPUDPport filterITCH decoderA · X · E · UOrder tablefind, update, freeTop of bookmax bid, min askResult registerscounters, statusUARTto Python plot
Order table. Parallel arrays with a combinational search for the matching reference and a priority search for a free slot. Reductions saturate at zero and free the slot.
Illustrative. Packet bytes to top of book. Select a block for its role. Input is software packet injection, not a live network feed.

What I did

I wrote the Ethernet, IPv4 and UDP parsers, an ITCH-style decoder, the order table and top-of-book logic, and an AXI4-Lite peripheral.

A MicroBlaze program injects test packets, including bad frames, and reports results over UART.

Result

  • On the board, valid packets update the book and invalid frames increment the drop counter.
  • Timing closed at 100 MHz on Spartan-7; about 13k LUTs and 280 mW for the build.
  • A controlled demo with software-injected packets, not a live feed or a trading engine.
  • Power is a build figure, not a bench measurement; no per-packet latency is claimed.

Design decision

Inject packets from software

A MicroBlaze program writes packet bytes into a FIFO. Every test is reproducible without a working network MAC, at the cost of a demo rate set by software, not the parser.

Try it

Step through the messages and watch the book update.

Empty book. No messages applied.

Messages

  1. A Add buy #1: 300 at 99
  2. A Add sell #2: 200 at 101
  3. A Add buy #3: 150 at 98
  4. A Add sell #4: 250 at 102
  5. A Add buy #5: 100 at 99
  6. X Cancel 150 from #3
  7. E Execute 120 against #2
  8. E Execute 80 against #2
  9. U Replace #5 with #6: 180 at 100
  10. A Add sell #7: 120 at 101
  11. X Cancel 100 from #1

Top of book

Best bid
none
Best ask
none

Depth by price tick

bids (buy) asks (sell)

Active orders

OrderSidePriceQty
No active orders.

Best prices by message

Illustrative. A declared message sequence, replayed. Synthetic protocol demonstration; not live trading data or a hardware benchmark. Replay speed is unrelated to the 100 MHz clock.

More detail

Layered parsing

Each header layer is checked and stripped before the message is decoded. A malformed frame is consumed to its end so the parser stays aligned.

Parsers and the order table

Each parser accepts a byte only when valid and ready are both high, so backpressure can't corrupt header offsets. The decoder packs big-endian fields into one structure.

Active orders sit in parallel arrays. After each update, logic finds the highest buy and lowest sell and sums the quantity at each. The top of book covers the whole table, not each symbol.

Testing

Testbenches covered Ethernet accept and drop, each order operation and its errors, register reads and integrated packet injection.

Other design decisions

  • Replace in two steps

    Remove the old order, then insert the new one in the next state. Instead of: both in one cycle.

    Avoids reusing a slot before it is visibly free, for one extra state.

  • UART instead of HDMI

    Print results over UART and plot them in Python. Instead of: the HDMI display tried early on.

    Dropping a fragile display path kept the focus on the book logic.

  • FPGA Edge DetectionLive camera video in, edge outlines out on HDMI, all in FPGA hardware across three clock domains.
  • Pipelined RISC-V CPUA five-stage RISC-V processor with forwarding, stalls and branch flushes, grown from a single-cycle design.