Jashwanth Bamidi

Jashwanth Bamidi

Computer Engineering / UIUC

I design circuit boards, bring them up on the bench, and write the firmware and FPGA logic that put them to work. I study Computer Engineering at Illinois.

Résumé, PDFjassubamidi24@gmail.com

Experience

  1. Archer Aviation

    Electrical Engineering Intern

    May – Aug 2026

    Designed the board and firmware for a network-controlled cooling-flow controller on inverter test stands. Also wired a 1000 V reliability stand and automated its setup.

  2. Eco Illini

    Power Distribution Unit Lead

    Aug 2025 – now

    Designed and laid out the car's four-layer power distribution board, then assembled and validated it in the vehicle. I also lead the PDU and Joule Meter teams.

  3. Spatial Audio

    Undergraduate Researcher

    Aug 2025 – now

    Research with Prof. Yu-Lin Wei on headphone audio that stays fixed in the room as you turn. I built the head-tracking and rendering pipeline and a head-pose predictor.

The Eco Illini power distribution board

My design and layout: a four-layer board that turns the car's 36 V battery into protected 12 V and 3.3 V supplies. It was fabricated, assembled and validated in the vehicle.

Design and testing

Three-quarter Blender render of the assembled Eco Illini power distribution board with yellow XT60 connectors, a labeled black relay, microcontroller, regulator circuitry, inductors and a labeled metal DC/DC module on a green PCB.
Render of the design file. Blender render from the e7 PDU rev. 0 geometry, with recreated component labels. L1 and F1 use representative models.

Selected projects

High Speed FPGA PCB

In progress · Planning

Planning a custom FPGA board with external DDR memory, several power rails and debug access, to learn how those constraints shape a board before fabrication.

Open questions

  • Which FPGA and memory pairing can be routed and assembled?
  • How should four low-voltage rails start up from 5 V?
  • What test access will isolate a first-power fault?

Planning notes

proposed board edgememory railcore, aux, I/Omemory bus5 V inputUSB-C or externalSource selectFour buck railscore, auxiliary, memory, I/OFPGAlogic and memory controllerDDR memoryexternal, x16Config flashJTAG and UARTTest pointsEthernetoptional
proposed board edge5 V inputUSB-C or externalSource selectFour buck railscore, auxiliary, memory, I/OFPGADDRexternal, x16Config flashJTAG and UARTTest pointsEthernetoptional
Proposed architecture. What the board is meant to hold. Functional blocks only; no layout, routing or stackup is fixed yet.
Three-quarter VisionVest render with a front-mounted camera phone, ultrasonic sensors, yellow tactile motors, an ESP32 powered by a USB power bank, and a separate 9 V battery connected to the motor driver.
Conceptual illustration. A vest that communicates by touch. Phone on the front, USB power bank for the ESP32, separate 9 V motor battery; mounting approximated. Video of the real prototype

VisionVest

Hackathon prototype, StarkHacks 2026

A vest that guides its wearer by touch. A phone camera picks a direction and the vest buzzes front, back, left or right. I built the vest's controller, sensors and motor drive.

  1. Phone picks a direction
  2. Vest drops stale commands
  3. Motor on that side buzzes

Command handling and demo

Hardware Guitar Tuner

Tells you whether a guitar note is sharp or flat using only analog circuits. I designed it on a breadboard and used test tones and a scope to find the wiring fault that broke it.

Illustrative oscilloscope screen: yellow CH1 is the 630 Hz filter and cyan CH2 is the 690 Hz filter, with a 660 Hz input, 500 microseconds per division and 500 millivolts per division on both channels.
Conceptual illustration. The two filter outputs, on a scope. Generated illustration; the traces are not measurements. Try the filter model

More work

  • FPGA Edge Detection

    Live camera video in, edge outlines out on HDMI, all in FPGA hardware across three clock domains.

    FPGA & digitalBuilt and demonstrated

  • FPGA Orderbook Engine

    Hardware that parses network packets and keeps a live best bid and ask, fed by software-injected test traffic.

    FPGA & digitalBuilt · controlled demonstration

  • Pipelined RISC-V CPU

    A five-stage RISC-V processor with forwarding, stalls and branch flushes, grown from a single-cycle design.

    FPGA & digitalBuilt and simulated

  • CUDA Attention Kernels

    GPU kernels that reorder attention tensors between token-major and head-major layouts, written for efficient memory access.

    DSP & GPUCoursework

All projects and earlier work

About and contact

I'm a Computer Engineering student at Illinois, graduating in May 2028. I like owning a board from block diagram to bench, and I'm looking for roles in PCB design, board bring-up and hardware test.