PCB & analog In progress · Planning
High Speed FPGA PCB
A planned FPGA board with external DDR memory, for learning what a high-speed memory interface demands before committing to a layout.
- USB-C, 5 Vsource detect
- External 5 V
- Source selectpriority, no back-feed
- Protected 5 V bus
- Core≈ 1.0 V buck
- Auxiliary≈ 1.8 V buck
- Memory≈ 1.35 V buck
- I/O≈ 3.3 V buck
- FPGASpartan-7 candidate
- DDR3L x16candidate
- Flash, JTAG, UART, test points
What is planned
Planned: an FPGA with x16 DDR3L memory, four buck rails from 5 V, configuration flash, JTAG and UART debug, test points, and possibly Ethernet.
Spartan-7 is the leading candidate; every part is still a candidate.
Current state
- Requirements, interface budget and candidate power tree drafted.Planned
- No completed schematic, layout, fabricated board or DDR measurement yet.
- Rail values and parts are preliminary.
Design decision
Plan for staged bring-up
Each rail gets its own enable, plus test points and debug access, so the first power-up can isolate one fault at a time. It costs parts and board area.
More detail
Why this board
My finished boards are power and control boards. A memory interface adds controlled impedance, byte-lane skew, reference planes, BGA escape and rails that must come up in order.
Planned power and memory
A protected 5 V bus, from USB-C or an external supply, feeds core, auxiliary, memory and I/O regulators. ECP5 is the alternative FPGA to evaluate.
Why bucks: an LDO from 5 V to 1 V at 0.5 A would waste 2 W to deliver 0.5 W.
Planned bring-up order
Inspection and resistance checks, current-limited first power, each rail and its sequencing, clock and reset, JTAG, then walking-bit and address memory tests, and later thermal and signal-integrity measurements.
Other design decisions
Use proven memory-controller IP
Evaluate vendor or open controller IP. Instead of: writing a controller.
Keeps the project about the board.